This application claims the benefit of Korean Patent Application No. 2001-46567, filed Aug. 1, 2001, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to integrated circuit devices and methods of operating same and, more particularly, to integrated circuit memory devices and methods of operating same.
A conventional integrated circuit memory device may include a high voltage generating circuit for generating a voltage higher than a power voltage. Devices using a battery as a power source may include a high voltage generating circuit for generating a voltage higher than a battery power voltage. A high voltage generating circuit of an integrated circuit memory device may generate a high voltage target of about 4 volts when an external power voltage is in a predetermined range, such as, for example, about 2.2 volts to about 2.8 volts.
As a level of a power voltage of a system incorporating an integrated circuit memory device is decreased, however, a level of an external power voltage applied to the integrated circuit memory device may also decrease. Accordingly, when an external power voltage less than, for example, about 2.2 volts is applied, the integrated circuit memory device""s high voltage generating circuit may not be able to generate a target voltage of about 4 volts.
In more detail, the integrated circuit memory device""s high voltage generating circuit may use a step-up capacitor having a specific side based on the assumption that an external power voltage is in a predetermined range. When an external power voltage falls below the expected voltage range, the high voltage generating circuit may generate a target voltage of about 4 volts by increasing the capacitance of the step-up capacitor. Unfortunately, increasing the size of the step-up capacitor may increase the layout area needed to accommodate the high voltage generating circuit.
A conventional high voltage generating circuit 100 will now be described with reference to FIG. 1. Signals and the media carrying those signals may be referred to by the same names. Referring now to FIG. 1, the conventional high voltage generating circuit 100 comprises first and second delay circuits 10 and 12, first and second level shifters 14 and 16, NOR gates NOR1 and NOR2, a NAND gate NA1, inverters I1 through I8, NMOS transistors NC1 through NC5, and NMOS transistors N1 through N7.
An external power voltage VEXT is applied to the first and the second delay circuits 10 and 12, the NOR gates NOR1 and NOR2, the NAND gate NA1, and the inverters I3 through I6. A high voltage VPP is applied to the inverters I1, I2, I7, and I8, and the first and second level shifters 14 and 16.
The first and the second delay circuits 10 and 12, the NOR gates NOR1 and NOR2, the first and the second level shifters 14 and 16, the NAND gate NA1, the inverters I1 through I8, the NMOS capacitors NC1 and NC2, and the NMOS transistors N1 and N2 comprise a circuit that generates control signals for controlling a voltage step-up operation of the high voltage generating circuit. The NMOS transistors N3, N4, and N6 comprise a circuit that pre-charges signals n8, n10, and n13 during a pre-charge operation. The NMOS capacitor NC3 and the NMOS transistor N5 comprise a first step-up circuit that steps-up the signal n10, which corresponds to a step-up node, during an active operation. The NMOS capacitor NC4 comprises a second step-up circuit that steps-up the signal n10 node during an active operation. The NMOS capacitor NC5 comprises a step-up circuit that steps-up the signal n13 during an active operation. The NMOS transistor N7 comprises a high voltage transmission circuit that transmits the signal n10 at the step-up node to a high voltage generation terminal during an active operation.
The first delay circuit 10 delays a pulse signal EN by a first delay time d1 to generate a signal n1. The second delay circuit 12 delays an output signal of the first delay circuit 10 by a second delay time d2 to generate a signal n2. The NOR gate NOR1 NORs the pulse signal EN and the signal n1 to generate a signal n3. The NOR gate NOR2 NORs the signals n2 and n3. The NAND gate NA1 and the inverter I6 AND the signals n2 and n3. The first and the second level shifters 14 and 16 level-shift levels of the output signals of the NOR gate NOR2 and the inverter I6, respectively. The inverter I1 inverts an output signal of the first level shifter 14 to generate a signal n4. The inverter I2 inverts an output signal of the inverter I1. The NMOS capacitor NC1 pre-charges a signal n5 to a level of the external power voltage VEXT in response to an output signal of the inverter I2. The NMOS transistor N1 generates a signal n5 at the external power voltage level VEXT in response to the signal n4. The inverter I3 inverts the signal n3 to generate a signal n7. The NMOS transistor N2 generates a signal n6 at the external power voltage level VEXT. The NMOS capacitor NC2 pre-charges the signal n6 to the external power voltage VEXT level in response to the signal n3. The NMOS transistor N3 generates a signal n8 at the external power voltage level VEXT in response to the signal n3. The NMOS capacitor NC3 steps up the signal n8 in response to the signal n7. The NMOS transistor N5 facilitates charge sharing between nodes n8 and n10 to step up the signal n10 in response to the signal n5. The NMOS transistor N4 generates the signal n10 at the external power voltage level VEXT in response to the signal n6. The inverters I4 and I5 delay the signal n2 to generate a signal n9. The NMOS capacitor NC4 steps up the signal n10 in response to the signal n9. The inverter I7 inverts an output signal of the second level shifter 16 to generate a signal n11. The inverter I8 inverts the signal n11 to generate a signal n12. The NMOS transistor N6 generates the signal n13 at the external power voltage level VEXT in response to the signal n11. The NMOS capacitor NC5 steps up the signal n13 in response to the signal n12. The NMOS transistor N7 facilitates charge sharing between the node n10 and the high voltage generation terminal in response to the signal n13.
FIG. 2 is a waveform diagram that illustrates operations of the conventional high voltage generating circuit 100 of FIG. 1. During a time period t1, the external power voltage VEXT is applied and the pulse signal EN is at a common or ground voltage level VSS. The first delay circuit 10 delays the pulse signal EN by a first delay time d1 to generate a signal n1 at the ground voltage level VSS. The second delay circuit 12 delays the signal n1 by a second delay time d2 to generate a signal n2 at the ground voltage level VSS. The NOR gate NOR1 NORs the pulse signal EN and the signal n2 to generate a signal n3 at the external power voltage level VEXT. The NOR gate NOR2, the first level shifter 14, and the inverter I1 receive the signals n2 and n3 to generate the signal n4 at the high voltage level VPP. The NMOS transistor N1 pre-charges the signal n5 to the external power voltage level VEXT in response to the signal n4. The inverter I3 inverts the signal n3, which is at the external power voltage level VEXT, to generate the signal n7 at the ground voltage level VSS. The NMOS transistor N2 pre-charges the signal n6 to the external power voltage level VEXT. The NMOS capacitor NC2 steps up the signal n6 to a voltage of 2VEXT when the signal n3 is driven to the external power voltage level VEXT. The NMOS transistors N3 and N4 pre-charge the signals n8 and n10 to the external power voltage level VEXT, respectively, when their gate terminals are driven to a voltage level of 2VEXT. The inverters I4 and I5 generate the signal n9 at the ground voltage level VSS in response to the signal n2. The NAND gate NA1, the inverter I6, the second level shifter 16, and the inverter I7 generate the signal n11 at the high voltage level VPP in response to the signals n1 and n2. The inverter I8 generates the signal n12 at the ground voltage level VSS in response to the signal n11. The NMOS transistor N6 pre-charges the signal n13 to the external power voltage level VEXT in response to the signal n11.
During a time period t2 that the pulse signal EN transitions from the ground voltage level VSS to the external power voltage level VEXT, the first delay circuit 10 delays the pulse signal EN by the first delay time d1 to generate the signal n1 at the external power voltage level VEXT. The second delay circuit 12 delays the signal n1 by the second delay time d2 to generate the signal n2 at the external power voltage VEXT level. The NOR gate NOR1 NORs the signals n1 and n2 to generate the signal n3 at the ground voltage level VSS. The NOR gate NOR2, the first level shifter 14, and the inverter I1 generate the signal n4 at the ground voltage level VSS in response to the signal n3. The inverter I2 inverts the signal n4 to generate a signal at the high voltage level VPP. The NMOS capacitor NC1 steps up the signal n5 to a voltage of xe2x80x9cVEXT+VPPxe2x80x9d in response to the signal at the output of the inverter I2. The NMOS capacitor NC3 steps up the signal n8 to a voltage of 2VEXT in response to the signal n7 being driven to the external power voltage level VEXT. The inverters I4 and I5 generate the signal n9 at the ground voltage level VSS in response to the signal n2. The NAND gate NA1, the inverter I6, the second level shifter 16, and the inverter I7 generate the signal n11 at the high voltage level VPP in response to the signals n1 and n2. The NMOS transistor N6 is turned on and drives the signal n13 to the external power voltage level VEXT in response to the signal n11. The inverter I8 inverts the signal n11 to generate the signal n12 at the ground voltage level VSS.
Because the NMOS transistors N4 and N7 are turned off and the NMOS transistor N5 is turned on during the time period t2, charge is shared between the nodes n8 and n10. As a result, the signal n8 is driven to a voltage 1.5VEXT and the signal n10 is driven a level of 1.5VEXT. Thus, a first step-up operation is performed on the signal n10.
During a time period t3, the signal n4 is transitions to the high voltage level VPP, the signal n5 transitions to the external power voltage level VEXT, the signal n9 transitions to the external power voltage level VEXT, and the signal n13 transitions to a voltage level of xe2x80x9cVEXT+VPPxe2x80x9d. The signals n6 and n7 are at the external power voltage level VEXT. As a result, the NMOS capacitor NC4 steps up the signal n10 to a voltage level of 2.5VEXT in response to the signal n9. At this moment, the NMOS transistors N4 and N5 are turned off, and the NMOS transistor N7 is turned on, so that charge sharing is performed between the node n10 and the high voltage generating terminal, which results in the signal n10 transitioning from the voltage 2.5VEXT to the high voltage level VPP. The signal n8 maintains a voltage level of 1.5VEXT.
After the time period t3, operations of the time periods t1 through t3 described above may be repeatedly performed to generate the high voltage VPP. In summary, the conventional high voltage generating circuit 100 steps up the node n8 from a voltage VEXT to a voltage 2VEXT and the node n5 from a voltage VEXT to a voltage xe2x80x9cVEXT+VPPxe2x80x9d during the second time interval t2 to turn on the NMOS transistor N5, to allow charge sharing between the nodes n10 and n8. This charge sharing operation steps up the voltage level at the node n10 to 1.5VEXT.
Thereafter, the node n9 transitions from the ground voltage level VSS to the external power voltage level VEXT to step up the voltage at the node n10 to 2.5VEXT using the NMOS capacitor NC4. Also, the node n13 is driven from the external power voltage level VEXT to a voltage of xe2x80x9cVEXT+VPP,xe2x80x9d which turns the NMOS transistor N7 on to allow charge sharing between the node n10 and the high voltage generating terminal VPP. The amount of charge transferred may be given by xe2x80x9cNC4xc3x97(2.5VEXTxe2x88x92VPP).xe2x80x9d After a second step-up operation is performed at the node n10, a voltage of the node n13 falls to the external power voltage level VEXT, which turns the NMOS transistor N7 off. The NMOS transistors N3 and N4 again precharge the signals n8 and n10 to the external power voltage level VEXT, respectively, when their gate terminals are driven to a voltage level of 2VEXT.
Typically, the sizes of the step-up capacitors NC3 and NC4 are set based on an assumption that the external power voltage VEXT is in a predetermined range. When the external power voltage VEXT is below the expected voltage range, then the conventional high voltage generating circuit can generate a high voltage target by increasing the capacitances of the step-up capacitors NC3 and NC4. Unfortunately, increasing the size of one or both of the step-up capacitor may increase the layout area needed to accommodate the high voltage generating circuit 100.
According to some embodiments of the present invention, a voltage generation circuit generates an output voltage at an output node thereof by sharing charge between a first node and a second node so as to increase a potential at the second node from a first voltage to a second voltage. The first node is charged to a third voltage and the second node is driven to a fourth voltage that is greater than the third voltage. Charge is shared between the first node and the second node so that the first and second nodes reach a common fifth voltage, which is between the third and fourth voltages. The first node is driven to a sixth voltage, which is greater than the fourth voltage. Charge is shared between the first node and the output node to generate the output voltage thereat. Advantageously, by sharing charge between the first node and the second node to increase the potential of the second node, the second node may be driven to a relatively high voltage, i.e., the fourth voltage described above, without the need to increase a size of a capacitor that may be used to drive the second node.
In other embodiments of the present invention, a capacitor may be used to drive the second node to the fourth voltage and/or a capacitor may be sued to drive the first node to the sixth voltage.
In still other embodiments of the present invention, charge may be shared between the first node and the second node to increase the potential at the second node from the first voltage to the second voltage by generating a first control signal and closing a switch between the first node and the second node responsive to the first control signal.
In still further embodiments of the present invention, charge may be shared between the first node and the second node so that the first and second nodes reach the common fifth voltage by generating a second control signal and closing the switch between the first node and the second node responsive to the second control signal.
Although embodiments of the present invention have been described above primarily with respect to method embodiments, voltage generation circuit embodiments are also provided.